Notgate

• 来源：Notgate - HDLBits

Problem Statement

Create a module that implements a NOT gate.

This circuit is similar to wire, but with a slight difference. When making the connection from the wire in to the wire out we're going to implement an inverter (or "NOT-gate") instead of a plain wire.

Use an assign statement. The assign statement will continuously drive the inverse of in onto wire out.

Tip

Verilog has separate bitwise-NOT (~) and logical-NOT (!) operators, like C. Since we're working with a one-bit here, it doesn't matter which we choose.

Official Solution

module top_module(
    input in,
    output out
);

    assign out = ~in;

endmodule

My Solution

module top_module( input in, output out );

    assign out = ~in;

endmodule