Exams/m2014 q4g

• 来源：Exams/m2014 q4g - HDLBits

Problem Statement

Implement the following circuit:

My Solution

module top_module (
    input in1,
    input in2,
    input in3,
    output out);

    assign out = in3 ^ (~(in1 ^ in2));

endmodule

Note

• 图中左边是同或门，右边是异或门
• 异或门使用^运算符