Mt2015 q4

• 来源：Mt2015 q4 - HDLBits

Problem Statement

Taken from 2015 midterm question 4

See mt2015_q4a and mt2015_q4b for the submodules used here. The top-level design consists of two instantiations each of subcircuits A and B, as shown below.

Implement this circuit.

Tip

You may choose to create this circuit hierarchically using the two submodules as shown in the diagram, or create the same functionality without hierarchy.

Official Solution

module top_module(
    input x,
    input y,
    output z);

    wire o1, o2, o3, o4;

    A ia1 (x, y, o1);
    B ib1 (x, y, o2);
    A ia2 (x, y, o3);
    B ib2 (x, y, o4);

    assign z = (o1 | o2) ^ (o3 & o4);

    // Or you could simplify the circuit including the sub-modules:
    // assign z = x|~y;

endmodule

module A (
    input x,
    input y,
    output z);

    assign z = (x^y) & x;

endmodule

module B (
    input x,
    input y,
    output z);

    assign z = ~(x^y);

endmodule

My Solution

module top_module (input x, input y, output z);

    reg z_IA1,z_IB1,z_IA2,z_IB2;
    reg z_or,z_and;

    A IA1(
        .x(x),
        .y(y),
        .z(z_IA1)
    );

    A IA2(
        .x(x),
        .y(y),
        .z(z_IA2)
    );

    B IB1(
        .x(x),
        .y(y),
        .z(z_IB1)
    );

    B IB2(
        .x(x),
        .y(y),
        .z(z_IB2)
    );

    assign z_or = z_IA1 | z_IB1;
    assign z_and= z_IA2 & z_IB2;
    assign z = z_or ^ z_and;

endmodule

module A (input x, input y, output z);

    assign z = (x ^ y) & x;

endmodule

module B ( input x, input y, output z );

    assign z = x & y | ~x & ~y;

endmodule