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Mt2015 eq2

Problem Statement

Taken from 2015 midterm question 1k

Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and produces an output z. The value of z should be 1 if A = B, otherwise z should be 0.

Official Solution

module top_module(
    input [1:0] A,
    input [1:0] B,
    output z);

    assign z = (A[1:0]==B[1:0]);    // Comparisons produce a 1 or 0 result.

    // Another option is to use a 16-entry truth table ( {A,B} is 4 bits, with 16 combinations ).
    // There are 4 rows with a 1 result.  0000, 0101, 1010, and 1111.

endmodule

My Solution

module top_module ( input [1:0] A, input [1:0] B, output z ); 

    always @(*) begin
        if(A == B)
            z = 1'b1;
        else
            z = 1'b0;
    end

endmodule

Note

  • 报错： 
    Error (10170): Verilog HDL syntax error at top_module.v(3) near text: "if";  expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword.
  • 搜索了发现是因为if语句需要在always块里面才能运行。
  • 官方答案给的方法就不需要使用if语句，代码就很简洁。